Wednesday, Jan 6, 2016
10:50-13:00	Session W/C-1: Interactive Presentation Papers
10:50-10:55	W/C-1.1	A Fast Settling 4.7 – 5 GHz Fractional-N Digital Phase Locked Loop.
		Pallavi Paliwal, Jaydip Fadadu, Anil Chawda, Shalabh Gupta
10:55-11:00	W/C-1.2	A 12.5 Gbps one-fifth rate CDR incorporating a novel sampler based phase detector and a DFE.
		Pragya Maheshwari, Suhas Kaushik, Mahendra Sakre, Shalabh Gupta
11:00-11:05	W/C-1.3	A -40 dBm input sensitive RF to DC converter CMOS rectifier for energy harvesting applications.
		Shouri Chatterjee, Mohd Tarique
11:05-11:10	W/C-1.4	A Digitally Assisted Radiation Hardened Current Steering Digital-to-Analog Converter.
		Abishek T. K., Bibhudatta Sahoo
11:10-11:15	W/C-1.5	Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
		Harsh Patel, Farah Yahya, Benton Calhoun
11:15-11:20	W/C-1.6	Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors.
		Sudarshan Srinivasan
11:20-11:25	W/C-1.7	Adaptive Voltage Frequency Scaling using Critical Path Accumulator implemented in 28nm CPU..
		Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger
11:25-11:30	W/C-1.8	A Hybrid Energy Efficient Digital Comparator.
		Syed Ahmed, Srinivas M.B., Sweekurth Srinivas
11:30-11:35	W/C-1.9	Modeling of Linear Variable Differential Transformer.
		Debashis Sahu, Siddhartha Hazra, Prajit Nandi
11:35-11:40	W/C-1.10	Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor.
		Chandan Yadav, Amit Agarwal, Yogesh Singh Chauhan
11:40-11:45	W/C-1.11	Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library
		Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman
11:45-11:50	W/C-1.12	Towards Designing Reliable Universal QCA Architectures in the presence of Cell Deposition Defect.
		Bibhash Sen, Rijoy Mukherjee, Yashraj Sahu, Rajdeep K Nath, Biplab K Sikdar
11:50-11:55	W/C-1.13	Ultra-low Power Wireless Sensor Network SoC for Biosignal Sensing Application in 65nm CMOS.
		Jaeyoung Kim, Nan Zheng, Yalcin Yilmaz, Pinaki Mazumder
11:55-12:00	W/C-1.14	FPGA-Based Design of a Hearing Aid with Frequency Response Selection through Audio Input.
		Shankarayya G. Kambalimath, Prem C. Pandey, Pandurangarao N. Kulkarni, Shivaling S. Mahant-Shetti, Sangamesh G. Hiremath
12:00-12:05	W/C-1.15	Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard.
		Pavan Kumar Manchi, Roy Paily, Anup Kumar Gogoi
12:05-12:10	W/C-1.16	Design and simulation of microfluidic components towards development of a controlled drug delivery platform.
		Richa Mishra, Tarun Kanti Bhattacharyya, Tapas Kumar Maity
12:10-12:15	W/C-1.17	Using Tweaks To Design Fault Resistant Ciphers.
		Sikhar Patranabis, Debapriya Basu Roy, Debdeep Mukhopadhyay
12:15-12:20	W/C-1.18	BRAIN: BehavioR based Adaptive Intrusion detection in Networks: Using Hardware Performance Counters to detecting DDoS Attacks.
		Vinayaka Jyothi, Xueyang Wang, Sateesh K. Addepalli, Ramesh Karri
15:50:16:50	Session W/C-2: Interactive Presentation Papers
15:50-15:55	W/C-2.1	Test Generation for Hybrid Systems using Clustering and Learning Techniques.
		Sudhi Proch, Prabhat Mishra
15:55-16:00	W/C-2.2	Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling.
		Pallavi Das, Jitendra Yadav
16:00-16:05	W/C-2.3	Test Time Minimisation in Scan Compression Designs using Dynamic Channel Allocation.
		Sumitha Krishnamurthi, Jais Abraham, Shankar Umapathi
16:05-16:10	W/C-2.4	A Novel EPE aware Hybrid Global Route Planner after Floorplanning.
		Bapi Kar, Susmita Sur-Kolay, Chittaranjan Mandal.
16:10-16:15	W/C-2.5	MSimDRAM: Formal Model Driven Development of a DRAM Simulator.
		Debiprasanna Sahoo, Manoranjan Satpathy
16:15-16:20	W/C-2.6	Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier.
		Rahul Shrestha, Utkarsh Rastogi
16:20-16:25	W/C-2.7	RHyMe: REDEFINE HyperCell Multicore for Accelerating HPC Kernels.
		Saptarsi Das, Nalesh S, Kavitha Madhu, S.K. Nandy, Ranjani Narayan
16:25-16:30	W/C-2.8	Reconfiguration performance recovery method on optically reconfigurable gate arrays.
		Minoru Watanabe