- Call for Papers
- Call for Tutorials
- Call for Design Contest
- Call for User/Designer Track Submissions
- Call for embedded tutorials, special sessions, and panels
- Paper Submissions
- IEEE Manuscript Templates for Conference Proceedings
- Final Camera Ready Paper Submission
- Student Fellowship Application
- Faculty Fellowship Application
- Call for Contributions Poster
- RASDAT 2013
A User/Designer Track is being introduced for the first time in 2013 at the VLSI Design Conference. The track aims to bring to the conference real world experience of designing complex chips and is specifically targeted to EDA tool users and designers in the industry. The goal of this track is to provide a platform for the design community to present and discuss practical aspects of all stages of design - including architecture, system design, RTL implementation, circuit design, verification, CAD flows, timing closure, DFT and physical design - using actual chip implementations as examples. The papers presented at this track should help designers gain insight into tricks and techniques that can be readily adopted to simplify design processes, possibly using design flows which require adoption of tools from multiple vendors.
To this end, we invite proposals for presentations for the User/Designer Track to both, share your knowledge and experience, and participate in the exchange of ideas in the designer community. The accepted proposals only need a lecture or a poster presentation at the conference, and do not require a completed paper to appear in the conference proceedings.
Email: Nagi.Naganathan@lsi.com
Email: jkhare@apm.com
Submissions : 24th August, 2012
Notification of acceptance : 19th October, 2012
Poster/Presentation submission : 30th November, 2012
secretary@vlsidesignconference.org
Click here to Submit
To this end, we invite proposals for presentations for the User/Designer Track to both, share your knowledge and experience, and participate in the exchange of ideas in the designer community. The accepted proposals only need a lecture or a poster presentation at the conference, and do not require a completed paper to appear in the conference proceedings.
Front End Design:
- RTL Design & Synthesis, Low Power Design, Power/Area/Performance Trade-offs
- Mixed-Signal and RF Design
- Architectural exploration & optimization (ESL or TLM)
- Embedded Hardware-Software Co-Design
- Design and Verification of IPs
- Various aspects of Verification (Assertion, Coverage, HVL Testbenches)
- Design Methodologies and Tool Flows
- Design for Test
Back End Design:
- Physical Design Closure
- Timing Analysis and Optimization
- Floor Planning and Physical Synthesis
- Reliability, Design For Manufacturing (DFM)
- Silicon Debug and Manufacturing Test
- Multi-chip Modules
- Package Design
- A Title
- Name, affiliation, phone number and email addresses along with a short biographical sketch and expertise for all authors
- An introduction on the practical aspect of the contribution
- A summary that highlights the specific contribution (practical aspects of the problem, techniques that work and do not work)
- References, if appropriate
For additional details, please contact the User/Design Track Chairs
Nagi Naganathan
LSI Corp, Allentown, PAEmail: Nagi.Naganathan@lsi.com
Jitendra Khare
Applied Micro, Sunnyvale, CAEmail: jkhare@apm.com
Notification of acceptance : 19th October, 2012
Poster/Presentation submission : 30th November, 2012
User Track Committee
| Name | Affiliation | Country |
| C. Srinivasan | Cosmic Circuits | India |
| Shankar Hemmady | Synopsys | US |
| Rajiv Joshi | IBM | US |
| Ram Krishnamurthy | Intel | US |
| S. Karthik | ADI | India |
| Jayanta Lahiri | ARM | India |
| Brian Bailey | EE Times | US |
| Bhanu Kapoor | Mimasic | US |
| Sreejit Chakravarthy | LSI | US |
| Srini Venkataramanan | CVCBLR | India |
| Jayendra Dwaraka | LSI | India |
| Bala Balasubramanian | LSI | US |
| Charutosh Dixit | LSI | US |